1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor integrated circuits, and more particularly to a structure and method for forming contact vias in semiconductor integrated circuits.
2. Description of the Prior Art
Conductive interconnect layers typically have an enlarged area in the layer itself at a location where a contact is to be made from a later formed interconnect layer. Those skilled in the art commonly call the enlarged area the enclosure. Recognizing that errors in mask alignment can shift a contact from a desired location, the enclosure accounts for errors in mask alignment by providing additional contact space. Thus, the enclosure ensures a contact will be made to an underlying interconnect layer.
A conflict arises, however, between the need for enclosures and the desire to reduce the chip sizes in integrated circuits. Those skilled in the art will recognize that there must be a minimum amount of space between adjacent conductive elements. Enclosures in an interconnect layer forces the distance between adjacent conductive elements to increase in order to maintain the minimum distance between the adjacent conductive elements. Thus, the need for enclosures places restrictions on how small the size of an integrated circuit can be.
Errors in mask alignment can also cause problems during formation of contact vias. Some contact vias are formed directly above an underlying conductive interconnect layer, and ideally, the contact lies on or touches only the underlying conductive interconnect layer. Errors in mask alignment, however, allow for placement of the contact via to shift from the desired location. And, because formation of contact vias typically requires overetching an insulating layer to ensure all material is removed from the contact via, underlying layers may be damaged during formation of the contact via.
Furthermore, this overetching combined with an error in mask alignment may create small geometric spaces between the conductive interconnect layer and the insulating layer. Those skilled in the art will recognize that it is sometimes difficult to fill in those small geometric spaces. This may cause voids or other defects within the contact, thereby affecting the integrity of the contact and the reliability of the integrated circuit.
Therefore, it would be desirable to provide a method for forming contact vias which protects underlying layers from damage during formation of the contact vias. It is also desirable that such a method form contacts which are free from voids or other defects. Finally, it is desirable that such a method eliminate the need for enclosures in conductive interconnect layers.